By Aaron Buchwald, Ken Martin

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A practical clock recovery circuit will require some type of frequency acquisition aid. A PLL-based clock recovery circuit is only capable of pulling-in a frequency error of the same order of the closed-loop bandwidth, which is typically a factor of 1000 less than the bit-rate. 1% over all processing and temperature variations, which is quite a stringent specification. A third clock recovery circuit that was adopted for application to 10-Gb/s systems is known as a data transition tracking loop (DTTL) [39, 40].

Since there is a positive portion to precisely cancel a negative portion of the signal in a time T , the correlation of these harmonic tones with the data pulse (the integral of the product of the tone with the data signal) is easily seen to be zero. Therefore, one would expect to find nulls in the PSD of the data steam at integer multiples of the bit-rate. Further, we can consider the contribution to the correlation integral when the frequency of the tone is increased. 3 shows the data pulse superimposed with two tones of different frequencies.

IEEE J. Select. , SAC-9(5):636–644, June 1991. [10] Hiroshi Hamano, Takuji Yamamoto, Yoshinori Nishizawa, Akinori Tahara, Norihito Miyoshi, Kouichi Suzuki, and Akihito Nishimura. High-speed Si-bipolar IC design for multi-Gb/s optical receivers. IEEE J. Select. , SAC-9(5):645–651, June 1991. 23 24 Integrated Fiber-Optic Receivers [11] Jens N. Albers and Hans-Ulrich Schreiber. A Si-bipolar technology for optical fiber transmission rates above 10 Gb/s. IEEE J. Select. , SAC9(5):652–655, June 1991.

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