By Anders Nilsson.

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Additional resources for Design of programmable multi-standard baseband processors

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1 Scope of the dissertation The scope of this dissertation is programmable baseband processors and how they can be designed to achieve a low power consumption and small silicon area. Special attention has been paid to four distinct areas of baseband processor design: • System architecture, including hardware/software partitioning and instruction set design. 2 Organization 5 • Selection and design of execution units and accelerators. • Multi-standard support. • Scheduling and instruction issue. The over-all goal has been to find low power and low clock rate processor solutions.

In outdoor systems the delayspread is often in the range of several micro-seconds, which further limits the symbol rate. Common reference “channels” are specified by various institutes and standardization organs to be used in benchmarking of channel equalizers. 1, two common channels are presented, the ITU Pedestrian A and ITU Vehicular Channel Model B [1]. The channel models represent a user walking 3 km/h in an urban environment and traveling in a car at 60 km/h respectively. The channel models specify a number of multi-path components (taps) with their delay and average power.

1, two common channels are presented, the ITU Pedestrian A and ITU Vehicular Channel Model B [1]. The channel models represent a user walking 3 km/h in an urban environment and traveling in a car at 60 km/h respectively. The channel models specify a number of multi-path components (taps) with their delay and average power. The phase and amplitude of the multi-path component are assumed to be Rayleigh distributed. The effects of multi-path-propagation and resulting inter-symbol interference are referred to as fading.

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