By Angela Krstic, Kwang-Ting (Tim) Cheng
In the early days of electronic layout, we have been fascinated by the logical correctness of circuits. We knew that if we bogged down the clock sign sufficiently, the circuit might functionality properly. With advancements within the semiconductor procedure expertise, our expectancies on pace have soared. a regularly requested query within the final decade has been how briskly can the clock run. This places major calls for on timing research and hold up trying out. Fueled by means of the above occasions, a big development has happened within the learn on hold up trying out. contemporary paintings contains fault types, algorithms for try out iteration and fault simulation, and techniques for layout and synthesis for testability. The authors of this e-book, Angela Krstic and Tim Cheng, have in my opinion contributed to this learn. Now they do a good larger carrier to the occupation by means of accumulating the paintings of a giant variety of researchers. as well as expounding this kind of good deal of knowledge, they've got introduced it with utmost readability. To additional the reader's figuring out many key innovations are illustrated by way of basic examples. the fundamental rules of hold up checking out have reached a degree of adulthood that makes them compatible for perform. In that experience, this publication is the simplest x hold up FAULT checking out FOR VLSI CIRCUITS to be had advisor for an engineer designing or checking out VLSI structures. Tech niques for course hold up trying out and to be used of slower attempt apparatus to check high-speed circuits are of specific interest.
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Extra resources for Delay Fault Testing for VLSI Circuits
1  gives the distribution of defect sizes for 91 out of 97 modules that failed the delay test. 1. 200 400 . - 1 2 1 2 • 600 800 1000 1200 1400 1600 1800 de1ay (ns) Fault size distribution in an IBM experiment. 8%) modules had delay defects of sizes between 1 and 100 ns, while 60 (or 66%) modules had delay defects of sizes between 1 and 200 ns. The failure analysis identified resistive first-layer-metal opens as the dominant cause of the delay defects. This experiment clearly shows the value and need for delay testing.
The proposed at-speed scheme can be used to detect them as well. Also, there exist faults that can be tested by both slow-fast-slow testing strategy and by the at-speed strategy. If these two strategies require that the circuit passes through a comparable number of states when testing a given fault, the at-speed scheme would clearly be superior in terms of the testing time. 4 SUMMARY Test application strategy is an integral part of delay test generation. This is especially true for testing sequential designs for which several different strategies exist.
Therefore, timing or pattern dependent defects represented 44% of all the defects in this experiment. 1 shows the test results for the circuits that 40 CHAPTER 4 have escaped at least one test. 1. Distribution of escapes for different test sets. Test set Num. of Number of defective escapes circuits tested delay at-speed s r s r f 6 6 10 4 8 5 7 18 11 16 9 16 9 34 27 2 3 2 7 2 34 27 1 2 2 7 2 Transition fault (Test 1) Transition fault (Test 2) 128 128 10 12 Gate delay (X -+ 0) Gate delay (X -+ rand) 88 88 17 13 16 128 128 69 69 69 69 69 35 27 7 8 7 12 8 35 27 5 5 10 4 35 28 4 5 3 10 4 Single stuck-at (Test 1, 100%) Single stuck-at (Test 2, 100%) 128 128 14 9 10 7 10 7 9 5 8 3 Pseudo-random/Exhaustive 128 7 2 3 1 1 Path Path Path Path Path Path Path delay delay delay delay delay delay delay (Crit.