By Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
This e-book used to be encouraged via the issues being confronted with shrinking IC approach characteristic sizes. it truly is renowned that as approach function sizes diminish, a number of electric difficulties like cross-talk, electromigration, self-heat, and so forth. have gotten very important. Cross-talk is likely one of the significant difficulties because it leads to unpredictable layout habit. particularly, it might bring about major hold up edition or sign integrity difficulties in a twine, reckoning on the nation of its neighboring wires. common techniques to take on the cross-talk challenge try to repair the matter as soon as it's created. In our procedure, we make sure that cross-talk is eradicated via layout. The paintings defined during this booklet makes an attempt to take an "outside-the-box" view and suggest a considerably various layout variety. This layout type first imposes a set structure development (or textile) at the built-in circuit, after which embeds the circuit being carried out into this textile. the material is selected rigorously so one can do away with the cross-talk challenge being confronted in modem IC approaches. With our selection of cloth, cross-talk among adjoining wires on an IC is diminished via among one and orders of importance. during this method, the cloth inspiration removes cross-talk up-front, and through layout. we suggest separate layout flows, each one of which makes use of the material inspiration to enforce good judgment. the 1st movement makes use of fabric-compliant common cells as an im plementation motor vehicle. We name those cells textile cells, they usually have an identical common sense performance as latest ordinary cells with which they're compared.
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Extra resources for Cross-Talk Noise Immune VLSI Design Using Regular Layout Fabrics
Global Clocking The common method of distributing clock signals on les is referred to as an H-tree. Such an H-tree structure is shaped like the letter "H", and is driven from the center of the "H". The clock signals at the endpoints of the vertical limbs of the "H" have the same arrival time since the total wire length from the center of the "H" to the endpoints is identical. This is true if the parasitic capacitances and inductances of each of the traces is identical, which is difficult to ensure in practice.
1. CROSS-TALK NOISE IMMUNE VLSI DESIGN Chip Area The main disadvantage of the DWF technique is that it could result in a larger chip-wide area utilization. This would seem intuitive, since signal wiring is performed at twice-minimum pitch. So wiring intensive circuits are likely to utilize more area. In Chapters 4 and 5, we introduce two design methodologies and compare the chip area utilization for DWF-based designs and standard cell-based designs. For the first methodology, which we call Fabric1, we obtain an area penalty of about 60% if two metal layers are utilized for routing.
Overview The problems faced in designing and manufacturing ICs using DSM fabrication processes are not entirely new. Over the past few years, these problems have slowly become significant enough that academia and industry have begun to take notice. As a result, techniques that address the cross-talk problem in DSM design are relatively recent. In this section we review some of the existing techniques which address cross-talk in DSM VLSI design. 2. 1 Ad-hoc Approaches Cross-talk is typically handled in an ad-hoc manner in industry [Grodstein, 1998].