By Robert W. Brodersen (auth.), Robert W. Brodersen (eds.)
A silicon compiler is a software program procedure that may instantly generate an built-in circuit from a user's specification.
Anatomy of a Silicon Compiler examines one such compiler intimately, overlaying the elemental framework and layout access, the particular algorithms and libraries that are used, the method of verification and trying out, behavioral synthesis instruments and a number of other purposes which show the system's functions.
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Extra resources for Anatomy of a Silicon Compiler
4. generate the structure_master view hierarchy using vb2oct. generate the structure_instance view hierarchy using DMoct. generate the Viewlogic wir files for each block using the oct2wir program. generate the viewlogic simulation file using the si v2vsm program. The first two steps are available from Viewlogic menus customized for LAGER. The last two steps can be automated as a side effect of the structure_instance view generation by specifying the oct2wir and siv2vsm programs as structure-processors in the appropriate schematics.
5 shows a pad frame created with the schematic interface for the TicTacToe chip. eTo. rrac. 4: Part of a top-level standard cell design schematic on the top level schematic are used by the Padgroup structure processor in creating the padframe. The FACET: prefix to a symbol attribute. For example. FACET:PAD=IO attaches that attribute as a property to the instance in the structure master view which corresponds to this symbol. The Padroute layout generator is used to construct the physical view of the padframe and to perform the pad to core routing.
As DMoct runs, diagnostics are output to indicate what DMoct is doing.