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Additional info for Advanced Xilinx Fpga Design With Ise
All Rights Reserved Too Many Logic Levels: Solutions • • • The implementation tools cannot do much to improve performance The netlist must be altered to reduce the amount of logic between flip-flops Possible solutions: – Check whether the path is a multi-cycle path • – – – If it is, add a multi-cycle path constraint Use the retiming option during synthesis to distribute logic more evenly between flip-flops Confirm that good coding techniques were used to build this logic (no nested IF or CASE statements) Add a pipeline stage Timing Closure with Timing Analyzer - 21 © 2003 Xilinx, Inc.
All Rights Reserved Timing Reports • Timing reports enable you to determine how and why constraints were not met – • The Project Navigator can create timing reports at two points in the design flow – – • Reports contain detailed descriptions of paths that fail their constraints Post-Map Static Timing Report Post-Place & Route Static Timing Report The Timing Analyzer is a utility for creating and reading timing reports Timing Closure with Timing Analyzer - 6 © 2003 Xilinx, Inc. All Rights Reserved Using the Timing Analyzer • • • Create and open a report in the Timing Analyzer by doubleclicking on Post-Place & Route Static Timing Report Open a plain text version of the report Start the Timing Analyzer to create custom reports by doubleclicking on Analyze Post-Place & Route Static Timing (Timing Analyzer) Timing Closure with Timing Analyzer - 7 © 2003 Xilinx, Inc.
All Rights Reserved Creating Custom Reports • • The Post-Map and Post-Place & Route Static Timing Reports are usually sufficient timing analysis tools Custom reports can be created with the Timing Analyzer to: – – – – *Show detailed path descriptions for more timing paths *Analyze specific paths that may be unconstrained Analyze designs that contain no constraints Change the constraints or design parameters to perform “what-if” analysis Timing Closure with Timing Analyzer - 25 © 2003 Xilinx, Inc.